DocumentCode :
2581944
Title :
A standard-cell placement tool for designs with high row utilization
Author :
Yang, Xiaojian ; Choi, Bo-Kyung ; Sarrafzadeh, Majid
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear :
2002
fDate :
2002
Firstpage :
45
Lastpage :
47
Abstract :
In this paper we study the correlation between wirelength and routability for standard-cell placement problem, under the modern place-and-route environment. We present a placement tool named Dragon (version 2.1), and show its ability to produce good quality placement for designs with high row utilization. Compared to an industrial placer and an academic state-of-the-art placer, Dragon can produce placement with better routability and shorter total wirelength. We describe many novel algorithmic details and implementation details of this placement tool. Experimental results show that minimizing wirelength improves routability and layout quality.
Keywords :
cellular arrays; circuit layout CAD; Dragon; high row utilization; industrial placer; layout quality; place-and-route environment; routability; standard-cell placement tool; wirelength; Analytical models; Circuit simulation; Circuit testing; Clustering algorithms; Computer science; Engines; Routing; Simulated annealing; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-1700-5
Type :
conf
DOI :
10.1109/ICCD.2002.1106746
Filename :
1106746
Link To Document :
بازگشت