DocumentCode :
2581962
Title :
K-time forced simulation: a formal verification technique for IP reuse
Author :
Roop, Partha S. ; Sowmya, A. ; Ramesh, S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Auckland Univ., New Zealand
fYear :
2002
fDate :
2002
Firstpage :
50
Lastpage :
55
Abstract :
Automatic IP (Intellectual Property) matching is a key to reuse of IP cores. This paper presents an IP matching algorithm that can check whether a given programmable IP block can be adapted to match a given specification. When such adaptation is possible, the algorithm also generates a device driver to adapt the IP block. Though simulation, refinement and bisimulation based algorithms exist, they cannot be used to check the adaptability of an IP block, which is the essence of reuse. The IP matching algorithm is based on a formal verification technique called k-time forced simulation proposed in this paper k-time forced simulation may be used for identifying whether a given IP block (a device D) can be adapted to match a specification (a function F), given that D has a clock that is k-times faster than F. We demonstrate the applicability of the algorithm by reusing several IP blocks.
Keywords :
bisimulation equivalence; circuit simulation; formal verification; hardware description languages; hardware-software codesign; industrial property; IP block; IP matching algorithm; bisimulation based algorithms; device driver; formal verification; intellectual property matching; k-time forced simulation; programmable IP block; Clocks; Distributed databases; Formal verification; Fuzzy logic; Intellectual property; Internet; Libraries; Productivity; Spatial databases; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-1700-5
Type :
conf
DOI :
10.1109/ICCD.2002.1106747
Filename :
1106747
Link To Document :
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