• DocumentCode
    2582156
  • Title

    BOOM: Enabling mobile memory based low-power server DIMMs

  • Author

    Yoon, Doe Hyun ; Chang, Jichuan ; Muralimanohar, Naveen ; Ranganathan, Parthasarathy

  • Author_Institution
    Intell. Infrastruct. Lab., Hewlett-Packard Labs., Palo Alto, CA, USA
  • fYear
    2012
  • fDate
    9-13 June 2012
  • Firstpage
    25
  • Lastpage
    36
  • Abstract
    To address the real-time processing needs of large and growing amounts of data, modern software increasingly uses main memory as the primary data store for critical information. This trend creates a new emphasis on high-capacity, high-bandwidth, and high-reliability main memory systems. Conventional and recently-proposed server memory techniques can satisfy these requirements, but at the cost of significantly increased memory power, a key constraint for future memory systems. In this paper, we exploit the low-power nature of another high volume memory component-mobile DRAM-while improving its bandwidth and reliability shortcomings with a new DIMM architecture. We propose Buffered Output On Module (BOOM) that buffers the data outputs from multiple ranks of low-frequency mobile DRAM devices, which in aggregation provide high bandwidth and achieve chipkill-correct or even stronger reliability. Our evaluation shws that BOOM can reduce main memory power by more than 73% relative to the baseline chipkill system, while improving average performance by 5% and providing strong reliability. For memory-intensive applications, BOOM can improve performance by 30-40%.
  • Keywords
    DRAM chips; buffer storage; circuit reliability; low-power electronics; memory architecture; power aware computing; BOOM; DIMM architecture; bandwidth improvement; baseline chipkill system; buffered output on module; chipkill-correct; data output buffering; dual in-line memory modules; high-capacity-high-bandwidth-high-reliability-main memory systems; high-volume memory component; low-frequency mobile DRAM devices; main memory power reduction; memory-intensive applications; mobile DRAM; mobile memory based low-power server; performance improvement; primary data storage; real-time processing; reliability improvement; Bandwidth; DRAM chips; Error correction codes; Mobile communication; Reliability; Servers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture (ISCA), 2012 39th Annual International Symposium on
  • Conference_Location
    Portland, OR
  • ISSN
    1063-6897
  • Print_ISBN
    978-1-4673-0475-7
  • Electronic_ISBN
    1063-6897
  • Type

    conf

  • DOI
    10.1109/ISCA.2012.6237003
  • Filename
    6237003