Title :
Analysis of the tradeoffs for the implementation of a high-radix logarithm
Author :
Pineiro, J.-A. ; Ercegovac, M.D. ; Bruguera, J.D.
Author_Institution :
Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain
Abstract :
An analysis of the tradeoffs between area and speed for a sequential implementation of a high-radix recurrence for logarithm computation is presented in this paper The high-radix algorithm is outlined and a sequential architecture is proposed, with the use of selection by rounding of the digits and redundant representation. Estimates of the execution time and total area are obtained for n = 16, 32 and 64 bits of precision and for radix values from r = 8 to r = 1024. An analysis of the tradeoffs between area and speed is presented, showing that the most efficient implementations are obtained for radices r = 256 for 16, 32 bit and r = 128 for 64 bit computations.
Keywords :
digital arithmetic; 32 bit; 64 bit; digit rounding; execution time; high-radix algorithm; high-radix logarithm; high-radix recurrence; logarithm computation; redundant representation; selection; sequential architecture; speed/area tradeoffs; total area; Algorithm design and analysis; Application software; Computer architecture; Computer networks; Computer science; Costs; Delay estimation; Hardware; Polynomials; Table lookup;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7695-1700-5
DOI :
10.1109/ICCD.2002.1106760
