High level estimation of the area and power consumption of on-chip interconnects

Author

Langen, Dominik ; Brinkmann, André ; Rückert, Ulrich

Author_Institution

Heinz Nixdorf Inst., Paderborn Univ., Germany

fYear

2000

fDate

2000

Firstpage

297

Lastpage

301

Abstract

This paper addresses the problem of estimating the power and area consumption of on-chip interconnects for standard cell ASIC processes. We introduce a set of analytic investigations on buses, crossbar switches, and multiplexors. Furthermore, we prove the accuracy of the results by comparing them with gate-level power-estimations on a double metal 0.6 μm CMOS technology

Keywords

CMOS digital integrated circuits; application specific integrated circuits; estimation theory; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; 0.6 micron; area consumption; buses; crossbar switches; double metal CMOS technology; high level estimation; multiplexors; onchip interconnects; power consumption; standard cell ASIC processes; CMOS technology; Decoding; Energy consumption; Integrated circuit interconnections; LAN interconnection; Libraries; Power system interconnection; Protocols; Switches; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6598-4

Type

conf

DOI

10.1109/ASIC.2000.880753

Filename

880753

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2582580