DocumentCode
2582661
Title
VLSI design and verification of the Imagine processor
Author
Khailany, Brucek ; Dally, William J. ; Chang, Andrew ; Kapasi, Ujval J. ; Namkoong, Jinyung ; Towles, Brian
Author_Institution
Comput. Syst. Lab., Stanford Univ., CA, USA
fYear
2002
fDate
2002
Firstpage
289
Lastpage
294
Abstract
The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford University and Texas Instruments in a 1.5 V 0.15 μm process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design a high-performance media processor in a modern ASIC flow.
Keywords
VLSI; digital signal processing chips; integrated circuit design; 0.15 micron; 1.5 V; ASIC flow; Al metal layers; Imagine stream processor; Stanford University; Texas Instruments; VLSI clocking; VLSI design; VLSI verification; high-performance media processor; transistor chip; Aluminum; Application specific integrated circuits; CMOS process; Collaboration; Design methodology; Instruments; Logic design; Monitoring; Streaming media; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-1700-5
Type
conf
DOI
10.1109/ICCD.2002.1106784
Filename
1106784
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