A spurious reduction technique for high-speed direct digital synthesizers

Author

Kushner, Lawrence J. ; Ainsworth, Marcus T.

Author_Institution

Lincoln Lab., MIT, Lexington, MA, USA

fYear

1996

fDate

5-7 Jun 1996

Firstpage

920

Lastpage

927

Abstract

Digital-to-Analog Converters (DACs) are the primary source of spurious in high-speed Direct Digital Synthesizers (DDS), DAC glitches, DC-linearity errors, and digital noise feedthrough can corrupt the DDS output. This paper proposes a balanced-DAC configuration at the DDS output that can dramatically reduce these effects. A pair of single-ended DACs are employed, driven from a set of inverters that generate the out-of-phase drive signals. An on- or off-chip subtractor combines the two out-of-phase DAC outputs, canceling distortion, noise, and glitches. Simulations along with experimental results from an 800 MHz balanced-DAC DDS breadboard are included. Greater than 10 dB reduction in harmonics, aliased-harmonics, and noise floor have been achieved. A monolithic version of this balanced-DAC DDS has been fabricated and is currently in test

Keywords

bipolar integrated circuits; digital-analogue conversion; direct digital synthesis; electric distortion; harmonics; integrated circuit noise; interference suppression; 800 MHz; DAC glitches; DC-linearity errors; DDS output; aliased-harmonics; balanced-DAC configuration; digital noise feedthrough; digital/analog converters; direct digital synthesizers; distortion; harmonics; high-speed DDS; monolithic version; noise floor; out-of-phase drive signals; single-ended DACs; spurious reduction technique; Clocks; Feedback loop; Frequency; Logic; Noise cancellation; Quantization; Read only memory; Synthesizers; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Frequency Control Symposium, 1996. 50th., Proceedings of the 1996 IEEE International.

Conference_Location

Honolulu, HI

Print_ISBN

0-7803-3309-8

Type

conf

DOI

10.1109/FREQ.1996.560276

Filename

560276