Title :
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
Author :
Tiri, Kris ; Verbauwhede, Ingrid
Author_Institution :
Dept. of Electr. Eng., UCLA, Los Angeles, CA, USA
Abstract :
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make ´new´ compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.
Keywords :
application specific integrated circuits; field programmable gate arrays; integrated circuit design; logic design; FPGA implementation; automated standard cell; crypto processor; logic level design methodology; power consumption; secure DPA resistant ASIC; Application specific integrated circuits; Capacitance; Cryptography; Design methodology; Energy consumption; Field programmable gate arrays; Libraries; Logic design; Logic gates; Resistance;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1268856
