Title :
Dynamic-threshold CMOS SRAM cells for fast, portable applications
Author :
Bhavnagarwala, Azeez J. ; Kapoor, Ashok ; Meindl, James D.
Author_Institution :
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER and lowers cell standby power by over an order of magnitude is proposed. These improvements are achieved by implementing a scheme of WL transition triggered pulses on source and substrate terminals of cell inverter transistors that share a common WL
Keywords :
CMOS memory circuits; SRAM chips; cellular arrays; integrated circuit noise; memory architecture; SER; WL transition triggered pulses; cell immunity; cell inverter transistors; cell read current; cell standby power; cell static noise margin; dynamic-threshold CMOS SRAM cells; portable applications; quad-rail CMOS SRAM cell architecture; Boosting; Capacitance; Geometry; Inverters; Large scale integration; MOSFET circuits; Random access memory; Subthreshold current; Threshold voltage; Transistors;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880764
