• DocumentCode
    2582806
  • Title

    A zero-overhead self-timed divider using new pipeline scheme

  • Author

    Yang, Jing-ling ; Choy, Chiu-Sing ; Chan, Cheong-Fat

  • Author_Institution
    Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    364
  • Lastpage
    368
  • Abstract
    This paper investigates the potential self-timed property of DCVSL circuits, and examines architecture techniques for providing self-timing in DCVSL circuits. As a result a new self-timed technique combined with high-speed dual-rail dynamic circuits is verified using a custom self-timed mantissa divider
  • Keywords
    asynchronous circuits; cellular arrays; dividing circuits; pipeline arithmetic; DCVSL circuits; high-speed dual-rail dynamic circuits; mantissa divider; pipeline scheme; zero-overhead self-timed divider; Circuits; Clocks; Computer architecture; Delay; Logic; Pipelines; Protocols; Rails; Signal generators; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
  • Conference_Location
    Arlington, VA
  • Print_ISBN
    0-7803-6598-4
  • Type

    conf

  • DOI
    10.1109/ASIC.2000.880765
  • Filename
    880765
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2582806