RightTopologizer: an efficient schematic generator for multi-level optimization

This paper presents an efficient algorithm for the automatic generation of schematic diagrams for digital systems described not only at the gate-level but also at the RTL. Schematics are generated in the sequence of pre-processing, topological placement, geometrical placement, and channel routing. The experimental results show that RightTopologizer produces more readable and compact schematics than a well-known commercial tool in a real time response. The high readability and compactness of the generated schematics helps the designers make early design decisions by providing a good grasp of signal flows which represent HDL-based designs. In addition, this system can be used for a multi-level optimization framework in a variety of applications due to using a common database with our schematic capture system