Efficient LDMOS device operation for envelope tracking amplifiers through second harmonic manipulation

In this work efficient LDMOS device operation for envelope tracking amplifier systems is discussed. Utilizing the voltage dependence of Cds in combination with a well chosen 2^nd harmonic output termination, a “hybrid” combination of class-J* and class-B device operation is defined, which yields improved efficiency at low supply voltages in power back-off, while avoiding device breakdown when operating at high supply voltages. Using these techniques with a Gen7 NXP 2W LDMOS device in a load-pull test bench, more than 63% drain efficiency over a 10 dB power back-off range is achieved at 2.14 GHz. The proposed method is supported by simulations and measurements and is directly applicable to envelope tracking power amplifiers.