Title :
Real time application architectural synthesis dedicated to sub-micron technologies
Author :
Jego, Christophe ; Casseau, Emmanuel ; Martin, Eric
Author_Institution :
Lab. Lester, Univ. de Bretagne Sud, Lorient, France
Abstract :
Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However, these tools do not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant with the technology decrease and the application complexity increase. A new methodology that enables the interconnection cost to be controlled all along the architectural synthesis process is presented in this paper
Keywords :
VLSI; application specific integrated circuits; circuit layout CAD; high level synthesis; integrated circuit interconnections; integrated circuit layout; real-time systems; ASIC design; VLSI interconnection cost control; area estimation; performance estimation; real time application architectural synthesis; real time constraints; submicron technologies; Arithmetic; Circuit synthesis; Costs; Design methodology; Flow graphs; Integrated circuit interconnections; Power dissipation; Space exploration; Space technology; Very large scale integration;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880771
