Title :
A new nanoelectronic based approach for efficient VLSI realization of SHA-512 algorithm
Author :
Shahmoradi, Abbas ; Masoumi, Massoud
Author_Institution :
ECE Dept., Semnan Univ., Semnan, Iran
Abstract :
This paper describes a preliminary performance evaluation of the implementation of Secure Hash Algorithm (SHA-512) building blocks on a cell-FPGA-like hybrid CMOS/nanodevice architecture. Such circuits will combine a semiconductor- transistor (CMOS) stack and a two-level nanowire crossbar with nanoscale two-terminal nanodevices (programmable diodes) formed at each crosspoint. The new design is based on two-cell fabric CMOL FPGA which can be used for mapping any arbitrary circuit. In addition, using a custom set of design automation tools quasi-optimium gate placing, placing, routing and rerouting are provided for SHA-512 fundamental building blocks. It is shown that such a design results in a circuit which is defect tolerant, much faster and strikingly denser than its CMOS counterpart.
Keywords :
CMOS digital integrated circuits; VLSI; cryptography; electronic engineering computing; field programmable gate arrays; file organisation; nanoelectronics; CMOS stack; SHA-512 algorithm; VLSI; arbitrary circuit; design automation tools; nanoelectronics; nanoscale two-terminal nanodevices; performance evaluation; programmable diodes; quasioptimium gate placing; rerouting; secure hash algorithm; two-cell fabric CMOL FPGA; two-level nanowire crossbar; CMOS digital integrated circuits; CMOS technology; Design automation; Fabrication; Fabrics; Field programmable gate arrays; NIST; Nanoscale devices; Routing; Very large scale integration; CMOL FPGA; CMOS FPGA; CMOS/Nanodevice Architecture; Nanoelectronic; Secure Hash Algorithm;
Conference_Titel :
EUROCON 2009, EUROCON '09. IEEE
Conference_Location :
St.-Petersburg
Print_ISBN :
978-1-4244-3860-0
Electronic_ISBN :
978-1-4244-3861-7
DOI :
10.1109/EURCON.2009.5167789
