DocumentCode :
2583035
Title :
Trace-level speculative multithreaded architecture
Author :
Molina, Carlos ; Gonzdalez, A. ; Tubella, Jordi
Author_Institution :
Dept. d´´Enginyeria Informatica i Maternatiques, Univ. Rovira i Virgili, Tarragona, Spain
fYear :
2002
fDate :
2002
Firstpage :
402
Lastpage :
407
Abstract :
This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectively. The architecture presents two main benefits: (a) no significant penalties are introduced in the presence of a misspeculation and (b) any type of trace predictor can work together with this proposal. In this way, aggressive trace predictors can be incorporated since misspeculations do not introduce significant penalties. We describe in detail TSMA (trace-level speculative multithreaded architecture) and present initial results to show the benefits of this proposal. We show how simple trace predictors achieve significant speed-up in the majority of cases. Results of a simple trace speculation mechanism show an average speed-up of 16%.
Keywords :
computer architecture; multi-threading; aggressive trace predictors; microarchitecture; misspeculation; speed-up; trace predictor; trace-level speculation; trace-level speculative multithreaded architecture; Buffer storage; Computer architecture; Counting circuits; Engines; Hardware; Microarchitecture; Proposals; Registers; Very large scale integration; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN :
1063-6404
Print_ISBN :
0-7695-1700-5
Type :
conf
DOI :
10.1109/ICCD.2002.1106802
Filename :
1106802
Link To Document :
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