Tunable impedance matching networks for agile RF power amplifiers

The efficiency is one of the most critical parameters in the design of RF power amplifiers. For classical power amplifier (PA) the efficiency drops dramatically in the back-off region. One possibility of enhancing the properties of the PA is the implementation of a load modulation as used in the Doherty topology. The idea of using an adaptive impedance matching network at the output of the transistor is presented and analyzed in this paper. The topology of the matching network enables the connection of the matching circuit directly to the transistor. The matching network has been designed using the minimum mean square error method and realized on a BST thick film substrate. The measured input impedance is in the range of several ohms for a load of 50Ohm as required for power amplifiers.