Title :
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Abstract :
The following are topics are dealt with: yield analysis and modeling; scan design and test data compression; reconfiguration; error correcting codes and circuits; fault detection; fault tolerance; sensors; flash memories; error tolerance; delay fault test and timing consideration; QCA circuits; interconnect test; soft errors; test scheduling; software-based test; analog circuit design and testing.
Keywords :
VLSI; analogue integrated circuits; error correction codes; fault diagnosis; fault tolerance; flash memories; integrated circuit design; integrated circuit interconnections; integrated circuit testing; integrated circuit yield; QCA circuits; VLSI systems; circuit design; circuit testing; delay fault test; error correcting circuits; error correcting codes; error tolerance; fault detection; fault tolerance; flash memories; interconnect testing; scan design; sensors; soft errors; software-based test; test data compression; test scheduling; yield analysis; yield modeling;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7695-2464-8
DOI :
10.1109/DFTVS.2005.2
