Title :
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
Author :
Bellato, M. ; Bernardi, P. ; Bortolato, D. ; Candelori, A. ; Ceschia, M. ; Paccagnella, A. ; Rebaudengo, M. ; Reorda, M. Sonza ; Violante, M. ; Zambolin, P.
Abstract :
This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.
Keywords :
SRAM chips; field programmable gate arrays; integrated circuit reliability; logic design; logic testing; radiation effects; ASIC; FPGA device; SEU; SRAM-based FPGA; configurable logic blocks; device configuration memory; field programmable gate arrays; programmable logic devices; radiation testing; route strategies; safety-critical environments; single event upsets; supporting tools; transient faults; CMOS technology; Circuits; Field programmable gate arrays; Predictive models; Programmable logic devices; Silicon; Single event transient; Single event upset; Testing; Transient analysis;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1268908
