Title :
Defects, yield, and design in sublithographic nano-electronics
Author :
Tahoori, Mehdi B.
Author_Institution :
Northeastern Univ., Boston, MA, USA
Abstract :
It is anticipated that defect densities in bottom-up self-assembled nanotechnology are much higher than those in conventional VLSI technologies. Therefore, defect tolerance needs to be included in various steps of the design automation flow. In this paper, a new defect tolerant flow is proposed and a new yield metric, based on this flow, is defined. This metric is evaluated for various molecular crossbars with different defect densities. Test and diagnosis of molecular crossbars, as the main building blocks in this technology, are also investigated.
Keywords :
fault tolerance; integrated circuit design; integrated circuit yield; nanoelectronics; bottom up self-assembled nanotechnology; defect densities; defect tolerance; defect tolerant flow; design automation flow; molecular crossbars; sublithographic nanoelectronics; yield metric; Circuits; Electronic equipment testing; Fabrication; Lithography; Molecular electronics; Nanoscale devices; Nanotechnology; Nanowires; Self-assembly; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
Print_ISBN :
0-7695-2464-8
DOI :
10.1109/DFTVS.2005.28
