Title :
Formal verification coverage: are the RTL-properties covering the design´s architectural intent?
Author :
Basu, Prasenjit ; Das, Sayantan ; Dasgupta, Pallab ; Chakrabarti, P.P. ; Mohan, Chunduri Rama ; Fix, Limor
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
It is essential to formally ascertain whether the RTL validation effort effectively guarantees the correctness with respect to the design´s architectural intent. The design´s architectural intent can be expressed in formal properties. However, due to the capacity limitation of formal verification, these architectural-properties cannot be directly verified on the RTL. As a result, a set of lower level RTL-properties are developed and verified against the RTL. In this paper we present: (1) a method for checking whether the RTL-properties are covering the architectural-properties, that is, whether verifying the RTL-properties guarantee the correctness of the design´s architectural intent; and (2) a method to identify the coverage holes in terms of the architectural properties (or their sub-properties) that are not covered.
Keywords :
formal verification; integrated circuit design; RTL validation; RTL-properties; architectural intent; formal verification; Automatic testing; Computer science; Design automation; Europe; Formal verification; Logic; Signal design; Strategic planning;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1268922