DocumentCode :
2583853
Title :
The other side of the timing equation: a result of clock faults
Author :
Metra, C. ; Omaña, M. ; Rossi, D. ; Cazeaux, J.M. ; Mak, T.M.
Author_Institution :
DEIS, Bologna Univ., Italy
fYear :
2005
fDate :
3-5 Oct. 2005
Firstpage :
169
Lastpage :
177
Abstract :
We analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven by Metra et al. (2004). Therefore, new testing/DFT approaches are needed to avoid the dramatic impact of clock faults on product quality and operation in the field. Various possible approaches are discussed.
Keywords :
circuit reliability; circuit testing; clocks; discrete Fourier transforms; fault tolerance; DFT approaches; clock faults; delay fault testing; delay violations; functional testing; structural testing; timing equation; Circuit faults; Clocks; Delay effects; Equations; Frequency; Manufacturing processes; Routing; Silicon; Testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
ISSN :
1550-5774
Print_ISBN :
0-7695-2464-8
Type :
conf
DOI :
10.1109/DFTVS.2005.65
Filename :
1544515
Link To Document :
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