DocumentCode :
2583875
Title :
Improving transition delay fault coverage using hybrid scan-based technique
Author :
Ahmed, Nisar ; Tehranipoor, Mohammad
Author_Institution :
ASIC Product Dev. Center, Texas Instruments India, Bangalore, India
fYear :
2005
fDate :
3-5 Oct. 2005
Firstpage :
187
Lastpage :
195
Abstract :
This paper presents a hybrid scan-based transition delay fault test. The proposed technique controls a small subset of scan cells by launch-off-shift method and the rest by launch-off-capture method. An efficient ATPG-based controllability measurement approach is proposed to select the scan cells to be controlled by launch-off-shift or launch-off-capture. In this technique, local scan enable signals are generated on-chip using two local scan enable generator cells. The cells can be inserted anywhere in a scan chain and the area overhead is negligible. The launch and capture information of scan enable signals are transferred into the scan chain during scan-in process. Our technique improves the fault coverage and reduces the pattern count and the scan enable design effort. The proposed hybrid technique is practice-oriented and implemented using current commercial ATPG tools.
Keywords :
automatic test pattern generation; boundary scan testing; fault diagnosis; integrated circuit reliability; integrated circuit testing; logic testing; ATPG controllability measurement; fault coverage improvement; hybrid scan-based transition delay fault test; launch-off-capture method; launch-off-shift method; scan chains; scan enable generator cells; scan-in process; transition delay fault coverage; Circuit faults; Circuit testing; Clocks; Controllability; Delay; Flip-flops; Instruments; Lab-on-a-chip; Product development; Signal generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
ISSN :
1550-5774
Print_ISBN :
0-7695-2464-8
Type :
conf
DOI :
10.1109/DFTVS.2005.69
Filename :
1544517
Link To Document :
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