DocumentCode
2583935
Title
QCA-based majority gate design under radius of effect-induced faults
Author
Patitz, Zachary D. ; Park, Nohpill ; Choi, Minsu ; Meyer, Fred J.
Author_Institution
Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA
fYear
2005
fDate
3-5 Oct. 2005
Firstpage
217
Lastpage
225
Abstract
This paper presents reliable QCA cell structures for designing single clock-controlled majority gates with a tolerance to radius of effect-induced faults, for use as a basic building component for carry look-ahead adder. Realizable quantum computing is still well in the future due to the complexity of the quantum mechanics that govern them. In this regard, QCA-based system design is a challenging task since each cell´s state must interact with all the cells that are in its energy-effective range in its clocking zone, referred to as its radius of effect. This paper proposes a design approach for majority gates to overcome the constraints imposed by the radius of effect of each cell with respect to clock controls. Radius of effect induces faults that lead to constraints on the clocking scheme of majority gates. We show majority gate structures that operate with multiple radius of effect-induced faults under a single clock control. The proposed design approach to a single clock controlled majority gate ultimately facilitate more efficient and flexible clocking schemes for complex QCA designs.
Keywords
adders; cellular automata; circuit reliability; clocks; fault diagnosis; fault tolerance; logic design; quantum gates; QCA cell structures; QCA designs; QCA-based majority gate design; QCA-based system design; carry look-ahead adder; effect-induced fault tolerance; flexible clocking schemes; quantum computing; quantum mechanics complexity; single clock-controlled majority gates; Automatic control; Circuit faults; Clocks; Computer architecture; Electrons; Electrostatics; Quantum cellular automata; Quantum computing; Quantum dots; Quantum mechanics;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2464-8
Type
conf
DOI
10.1109/DFTVS.2005.55
Filename
1544520
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