A Highly Reliable 0.35/spl mu/m Field-shield Body-tied SOI Gate Array For Substrate-bias-effect Free Operation

Author

Maeda, S. ; Yamaguchi, Y. ; Kim, I.-J. ; Iwamatsu, T. ; Ipposhi, T. ; Miyamoto, S. ; Hirano, Y. ; Ueda, K. ; Nii, K. ; Mashiko, K. ; Maegawa, S. ; Inoue, Y. ; Nishimura, T.

Author_Institution

Mitsubishi Electric Corporation, 4-l Mizuhara, Itami, Hyogo 664, Japan

fYear

1997

fDate

10-12 June 1997

Firstpage

Lastpage

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-75-1

Type

DOI

10.1109/VLSIT.1997.623711

Filename

623711

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