Parameters evaluation for SiC-JFET modeling considering non-uniformity by fabrication

Author

Cai, Chaofeng ; Qu, Yilong ; Guo, Qing ; Tao, Wang ; Sheng, Kuang

Author_Institution

Coll. of Electr. Eng., Zhejiang Univ., Hangzhou, China

fYear

2012

fDate

28-31 May 2012

Firstpage

437

Lastpage

441

Abstract

A method for evaluating the actual parameters of SiC-JFETs with good accuracy is presented. For precise SiC-JFETs modeling, accurate parameters have to be evaluated. During the simulation study, a significant discrepancy is observed between the simulation and measurement transfer characteristics, especially at gate biases close to its threshold value. In order to account for such discrepancy, probability distribution on device channel width across the whole device is modeled and incorporated into the Shockley model. The impact caused by nonuniformity of fabrication is computed and analyzed. Values of evaluated parameters are implemented into Saber, and great accuracy is verified by experimental transfer and forward on-state measurement.

Keywords

junction gate field effect transistors; probability; semiconductor device manufacture; semiconductor device models; silicon compounds; wide band gap semiconductors; JFET modeling; Saber; Shockley model; device channel; fabrication nonuniformity; forward on-state measurement; gate biases; measurement transfer; parameters evaluation; probability distribution; Fabrication; Integrated circuit modeling; JFETs; Logic gates; Probability distribution; Resistance; Silicon carbide; SiC-JFET; nonuniformity of fabrication; parameters evaluation; probability distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics (ISIE), 2012 IEEE International Symposium on

Conference_Location

Hangzhou

ISSN

2163-5137

Print_ISBN

978-1-4673-0159-6

Electronic_ISBN

2163-5137

Type

conf

DOI

10.1109/ISIE.2012.6237126

Filename

6237126