Title :
Highly noise-tolerant design of digital logic gates using Markov Random Field modelling
Author :
Anwer, Jahanzeb ; Khalid, Usman ; Singh, Narinderjit ; Hamid, Nor H. ; Asirvadam, Vijanth S.
Author_Institution :
Electr. & Electron. Eng. Dept., Univ. Teknol. PETRONAS, Tronoh, Malaysia
Abstract :
Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decreases the power dissipation of a circuit to a great extent, it decreases the signal to noise ratio as well. The need to transform the conventional logic gates into modified ones having the same functionality but are highly noise-tolerant is catered by the technique Markov Random Field (MRF) modelling proposed in [1]. This paper contributes towards explaining MRF design in a simplified form, proves the error tolerant capability of MRF circuits by simulations performed in Cadence (simulation software) and finally proposes an improvement in the design of [1].
Keywords :
CMOS logic circuits; Markov processes; logic gates; noise; CMOS transistor; Cadence; MRF circuit design; Markov Random field modelling; circuit power dissipation; digital logic gates noise-tolerant design; error tolerant capability; low supply voltage; signal to noise ratio; simulation software; CMOS digital integrated circuits; CMOS logic circuits; Circuit noise; Circuit simulation; Logic design; Logic devices; Logic gates; Low voltage; Markov random fields; Semiconductor device modeling; Markov random field; clique energy function; joint probability; logic compatibility function;
Conference_Titel :
Electronic Computer Technology (ICECT), 2010 International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7404-2
Electronic_ISBN :
978-1-4244-7406-6
DOI :
10.1109/ICECTECH.2010.5479997