Software-based self-test for pipelined processors: a case study

Software-based self-test (SBST) for processors and processor-based systems recently captured the interest of test technology researchers and practitioners due to its several advantages over traditional hardware built-in self-test (BIST). In this paper, we demonstrate for first time the full applicability of a recently proposed SBST methodology to a publicly available complex RISC processor implementation which includes a full pipelined architecture consisting of five pipeline stages, hazard detection, data forwarding and exceptions handling. We first show that the straightforward application of SBST routines developed for the nonpipelined version of the RISC processor can only reach a fault coverage less than 85% in the fully pipelined model. Then, we identify and classify areas with poor testability and provide solutions that extend the SBST methodology and achieve fault coverage more than 95% for this complex processor implementation.