Design of a CMOS operational amplifier amenable to extreme voltage stress

Extreme voltage stress (EVS) is an attractive burn-in technique employed in production test to weed out weak chips that may cause infant mortality. Application of this technique to analog integrated circuit (IC) has, however, only achieved limited success due to the significant irregularity in circuit topology. This paper examines the issue of design for EVS in analog IC and presents several analog circuit structures use of which enhances voltage stressability of analog circuits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18μm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with slight performance degradation.