DocumentCode
2584600
Title
A new test methodology for DNL error in flash ADCs
Author
Wieckowski, Michael ; Liobe, John ; Diduck, Quentin ; Margala, Martin
Author_Institution
Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
fYear
2005
fDate
3-5 Oct. 2005
Firstpage
582
Lastpage
590
Abstract
A novel test methodology is presented for characterizing DNL error in flash analog to digital converters. This test technique accurately measures the resistance of each resistor in the flash ladder and in turn, characterizes the DNL of a given chip. A testing time of approximately 1/2 ms is achieved with a 30% increase in area for a 6-bit flash ADC. When used in conjunction with standard automated test equipment, a reduction in total testing time and cost is predicted with minimal increase in area and power overhead.
Keywords
analogue-digital conversion; built-in self test; circuit testing; 6 bit; automated test equipment; differential nonlinearity errors; flash ADC; flash analog to digital converters; flash ladder; Analog-digital conversion; Built-in self-test; Circuit faults; Circuit testing; Computer errors; Costs; Electrical resistance measurement; Resistors; Signal design; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2464-8
Type
conf
DOI
10.1109/DFTVS.2005.11
Filename
1544558
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