• DocumentCode
    258492
  • Title

    An architectural approach for reconfigurable industrial I/O devices

  • Author

    Kirschberger, Daniel ; Flatt, Holger ; Jasperneite, Jurgen

  • Author_Institution
    Applic. Center Ind. Autom., Fraunhofer IOSB-INA, Lemgo, Germany
  • fYear
    2014
  • fDate
    8-10 Dec. 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper presents an architecture concept for reconfigurable industrial I/O devices. In order to avoid the use of special hardware modules as well as to offload the PLC from real-time preprocessing of sensor data, these tasks are shifted into the reconfigurable I/O device. Therefore, an FPGA based architecture template is proposed that supports loading of application-specific functions into the I/O device at runtime. The architecture template is partitioned into a static part and several reconfigurable slots. While the static part implements all fixed design elements, like the communication with the field bus and the in-system CPU, all application-specific functions are mapped onto the reconfigurable slots. In order to perform the reconfiguration of application-specific functions at runtime, the partial reconfiguration technology of modern FPGAs is used. The proposed concept is evaluated by mapping a case study with four reconfigurable slots onto a Xilinx Zynq-7000 SoC. The results show that new application-specific functions can be flexibly loaded into the I/O device. The total reconfiguration process of exemplary application-specific functions requires up to 3 ms and cause down-times below 0.5 ms. This especially enables new control applications that can even change the preprocessing within I/O devices during cyclic data communication.
  • Keywords
    field programmable gate arrays; reconfigurable architectures; system-on-chip; FPGA based architecture template; Xilinx Zynq-7000 SoC; architectural concept; reconfigurable industrial I/O device; static part; Automation; Computer architecture; Control systems; Field programmable gate arrays; Hardware; Performance evaluation; Runtime environment;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4799-5943-3
  • Type

    conf

  • DOI
    10.1109/ReConFig.2014.7032500
  • Filename
    7032500