Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC

Our proposed architecture of dynamically reconfigurable hardware for protocol processing (DRHPP) provides flexibility with high area efficiency. It can be used for a communications system-on-a-chip (SoC) in access networks. The DRHPP enables the modification and addition of various functions for protocol processing. Our architecture consists of three types of cells. The optimized number of these types of cells for the intended protocol processing can be implemented for increasing cell utilization, which can decrease the total area. Additionally, the best granularity for the cell also contributes to a decrease of the total area. We implemented a protocol-processing circuit using DRHPP for protocol-frame parser processing. Implementation results show the proposed architecture improves flexibility with only a 33% area penalty in comparison with a hard-wired protocol-processing circuit.