• DocumentCode
    258513
  • Title

    Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC

  • Author

    Quang-Hai Khuat ; Chillet, Daniel ; Hubner, Michael

  • Author_Institution
    INRIA, Univ. of Rennes 1, Rennes, France
  • fYear
    2014
  • fDate
    8-10 Dec. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper, we present a new online hardware/software (HW/SW) scheduling algorithm for a 3D Reconfigurable SoC platform comprising a multiprocessors layer and a heterogeneous reconfigurable layer. The proposed algorithm decides on the fly whether the tasks will run in SW or HW, at which time, on which processor or in which region of the reconfigurable layer in order to minimize the overall execution time of the application. It evaluates, during runtime, the interest to continue the SW execution of a task or to cancel it for starting a new HW execution of this task from the initial state. By using our algorithm called Hardware/Software algorithm with Software execution Prediction (HSSP), the overall execution time can be reduced by 26 % compared with other existing HW/SW scheduling methods.
  • Keywords
    hardware-software codesign; multiprocessing systems; processor scheduling; reconfigurable architectures; system-on-chip; 3D reconfigurable SoC platform; HSSP; HW execution; HW/SW scheduling algorithm; SW execution; dynamic run-time hardware/software scheduling; heterogeneous reconfigurable layer; multiprocessors layer; online hardware/software scheduling algorithm; software execution prediction; system-on-chip; Hardware; Scheduling; Scheduling algorithms; Software; Software algorithms; Three-dimensional displays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4799-5943-3
  • Type

    conf

  • DOI
    10.1109/ReConFig.2014.7032512
  • Filename
    7032512