• DocumentCode
    258532
  • Title

    FPGA-based accelerator development for non-engineers

  • Author

    Uliana, David ; Athanas, Peter ; Kepa, Krzysztof

  • Author_Institution
    Nat. Instrum. Corp., Austin, TX, USA
  • fYear
    2014
  • fDate
    8-10 Dec. 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In todays world of big-data computing, access to massive, complex data sets has reached an unprecedented level, and the task of intelligently processing such data into useful information has become a growing concern to the high-performance computing community. However, domain experts, who are the brains behind this processing, typically lack the skills required to build FPGA-based hardware accelerators ideal for their applications, as traditional development flows targeting such hardware require digital design expertise. This work proposes a usable, end-to-end accelerator development methodology that attempts to bridge this gap between domain-experts and the vast computational capacity of FPGA-based heterogeneous platforms. To accomplish this, a development flow was assembled, targeting the Convey Hybrid-Core HC-1 heterogeneous platform and utilizing an existing graphical design environment for design entry. The efficacy of the flow in extending FPGA-based acceleration to non-engineers in the life sciences was informally tested at an NSF-funded summer workshop, organized and hosted by a bioinformatics organization at a particular university. A group of five life-science-focused, non-engineer participants made significant modifications to a bare-bones Smith-Waterman accelerator, extending its functionality and improving performance.
  • Keywords
    Big Data; field programmable gate arrays; Convey Hybrid-Core HC-1 heterogeneous platform; FPGA-based accelerator development; FPGA-based heterogeneous platforms; NSF-funded summer workshop; big-data computing; bioinformatics organization; complex data sets; end-to-end accelerator development methodology; Acceleration; Bioinformatics; Computer architecture; Field programmable gate arrays; Hardware; Hardware design languages; Productivity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4799-5943-3
  • Type

    conf

  • DOI
    10.1109/ReConFig.2014.7032522
  • Filename
    7032522