Block-based hardware scheduler design on Many-core architecture

Because Moore´s law is always still working and the requirement of energy-saving still exists, CPU architecture is becoming more and more complicated and developing to Many-core architecture. But many-core is incompatible with the current programming mode designed for single-core CPU. This paper proposed a Block level Hardware-based Scheduling on many-core architecture (BHS) by adding the program control information which combined with hard-ware design. With BHS, many-core can execute a variety of parallel styles for suiting parallel granularity. The two main features of BHS are: First, a block-based hardware scheduler was implemented to reduce the overhead of threads and get communication among cores faster; second, it is very applicable to small and scalable cores which were tightly coupled in the cores group, loosely coupled between groups in many-core architecture. And a variety of parallel techniques would be effectively exploited.