Title :
Status of IEEE testability standards 1149.4, 1532 and 1149.6
Abstract :
Single board, and now multi-board testability is highly conditioned by the availability of various forms of boundary scan technology. This paper surveys the three more recent IEEE Standards relating to boundary scan. The paper is based on three backgrounders prepared by members of the individual Working Groups for the IEEE Standards booth at ITC 2003.
Keywords :
IEEE standards; boundary scan testing; IEEE testability standards; Institute of Electrical and Electronics Engineers; boundary scan technology; multiboard testability; Design for testability; Electronic design automation and methodology; Field programmable gate arrays; Jacobian matrices; Logic testing; Pain; Pins; Programmable logic arrays; Standards publication; Switches;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1269053
