Title :
Research of Stacked VIA´s Mechanical Stress
Author :
Nakanishi, Tohru ; Ohkuma, Hideo ; Ohira, Hiroshi
Author_Institution :
Nakanishi Prof. Eng. Office, Moriyama Shiga
Abstract :
The high density packaging has been focused with the Stacked via technologies. (The via is lettered as VIA hereafter because this is focused in this paper.) The stacked VIA technology becomes to be used for high density packaging as of today, however, it could not be said that the influence of the VIA stacking has been understood sufficiently. In this paper, the influence of one to five stacked VIA technologies are studied with the parameter of stress and strain on the view point of reliability, comparing the condition that these VIAs are located directly on the RFP (resin filled PTH (pin through hole)), and the other condition that these are located left and right with some distance from RFP. The guideline as to the optimized design of the substrate that has the stacked VIA is provided.
Keywords :
electronics packaging; reliability; stress-strain relations; high density packaging; mechanical stress; reliability; resin filled pin through hole; stacked VIA technology; Capacitive sensors; Chip scale packaging; Copper; Digital cameras; Materials reliability; Silicon; Surface treatment; Surface-mount technology; Thermal stresses; Wiring;
Conference_Titel :
Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, 2007. EuroSime 2007. International Conference on
Conference_Location :
London
Print_ISBN :
1-4244-1105-X
Electronic_ISBN :
1-4244-1106-8
DOI :
10.1109/ESIME.2007.359964
