DFT: Scan testing issues and current research

An inevitable consequence of technology scaling (and the resulting density growth of transistors) in IC design has been the increased power consumption in a chip during functional mode. Technology scaling has been accompanied by a linear reduction of supply voltage for the devices, but the exponential density increase of transistors allowed power density to continue its rapid ascent to levels that created two new obstacles: heat dissipation issues and power supply problems. These issues get magnified during the application of test techniques such as scan testing which is extensively used because it reduces test time and keeps test cost within a reasonable limit. Scan design is currently the most popular structured design for testability (DFT) method used in industry.