DocumentCode
2585948
Title
Automatic High Voltage Apparatus Optimization: Making it More Engineer-Friendly
Author
Trinitis, Carsten
Author_Institution
Inst. fur Inf., Technische Univ. Munchen
fYear
2006
fDate
13-17 Sept. 2006
Firstpage
20
Lastpage
30
Abstract
A key aspect in the design and optimization process of high voltage apparatus is the precise simulation and geometric optimization of the electric electromagnetic field distribution on electrodes and dielectrics. Since these simulations and optimizations are rather compute intensive, the engineer demands a user friendly working environment requiring as little knowledge as possible with regard to the computer specific aspects of the simulation and optimization process. Furthermore, the engineer demands the optimization run to finish as quickly as possible ("push button solution"), i.e. runtimes for extensive optimizations must be kept at an acceptable level. This paper describes a design and optimization working environment for high voltage apparatus that has been developed and implemented in a joint cooperation project between Technische Universitat Munchen and Asea Brown Boveri (ABB). Furthermore, some methods that enable the programmer accelerate and adapt the simulation program to specific CPU architectures are introduced. Three practical examples on which the working environment has been tested are presented
Keywords
cache storage; digital simulation; object-oriented programming; optimisation; power apparatus; power engineering computing; CPU architecture; cache optimization; electric electromagnetic field distribution; electric field simulation; high voltage apparatus; model driven architecture; Computational modeling; Computer simulation; Design optimization; Dielectrics; Electrodes; Electromagnetic fields; Knowledge engineering; Process design; Solid modeling; Voltage; Architecture; Cache Optimization; Electric field simulation; Model Driven; Optimization; Profiling;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on
Conference_Location
Bialystok
Print_ISBN
0-7695-2554-7
Type
conf
DOI
10.1109/PARELEC.2006.19
Filename
1698632
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