Packaging Effects of Cu/Low-k Interconnect Structure

A compressive study of packaging effects of Cu/low-k interconnect structure was represented in this paper by using finite element analysis. The modeling results of 3D-IC inter-wafer Cu/low-k interconnect structure were presented. Since the thermal deformation in 3D-IC package are usually coupled into Cu/low-k interconnect structure and inducing large local deformation to drive interfacial crack formation, the thermal reliability concerns for Cu/low-k chips are becoming the critical reliability issues in the present studies. Moreover, the associated thermal induced equivalent stresses could also result in failures to IC chip and affect its reliability. For the purpose of studying packaging effects of 3D-IC inter- wafer Cu/low-k interconnect structure, three-dimensional finite element analyses were used to analyze the thermal stresses distributions in Cu/low-k interconnect structure with complicated geometries. Furthermore, packaging induced crack driving forces for relevant interfaces in Cu/low-k interconnect structure were deduced. The modified virtual crack closure (MVCC) technique was used to calculate the energy release rate in 3D-IC inter- wafer Cu/low-k interconnect structure. The results not only show the existence of mix fracture mode at these interfaces in Cu/low-k interconnect structure but also indicate the significant packaging effect for 3D-IC inter- wafer Cu/low-k interconnect structure. In addition, the simulated results also show that the corresponding material properties of low-k dielectrics have prominent influences on thermal induced equivalent stresses.