DocumentCode :
2586141
Title :
Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks
Author :
Masko, Lukasz ; Mounie, Gregory ; Trystram, Denis ; Tudruj, Marek
Author_Institution :
Inst. of Comput. Sci., Polish Acad. of Sci., Warsaw
fYear :
2006
fDate :
13-17 Sept. 2006
Firstpage :
95
Lastpage :
100
Abstract :
The paper concerns task scheduling in dynamic SMP clusters based on the notion of moldable computational tasks. Such tasks have been used as atomic elements in program scheduling algorithms with warranty of schedule length. For program execution, a special shared memory system architecture is used. It is based on dynamic processor clusters, organized around shared memory modules by switching of processors between memory module busses. Fast shared data transfers between processors inside such clusters can be performed through data reads on the fly. The dynamic SMP clusters are implemented inside system on chip (SoC) modules additionally connected by a central global network. A task scheduling algorithm is presented for program macro dataflow graphs for execution in the assumed architecture. The algorithm first identifies a set moldable tasks in a given program graph. Next, this set is scheduled using a 2-phase algorithm including allotment of resources to moldable tasks and final list scheduling, with a warranty of schedule length. The complete algorithm has been implemented as a program package and examined using simulated execution of scheduled program graphs
Keywords :
data flow graphs; macros; parallel architectures; processor scheduling; resource allocation; shared memory systems; system-on-chip; workstation clusters; SoC modules; dynamic SMP clusters; dynamic processor clusters; macro dataflow graphs; program execution; program graph structuring; program scheduling algorithms; shared data transfers; shared memory system architecture; system-on-chip; task scheduling algorithm; Clustering algorithms; Computer architecture; Concurrent computing; Dynamic scheduling; Memory architecture; Processor scheduling; Read-write memory; Scheduling algorithm; System-on-a-chip; Warranties;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on
Conference_Location :
Bialystok
Print_ISBN :
0-7695-2554-7
Type :
conf
DOI :
10.1109/PARELEC.2006.69
Filename :
1698643
Link To Document :
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