A register allocation algorithm in the presence of scalar replacement for fine-grain configurable architectures

The aggressive application of scalar replacement to array references substantially reduces the number of memory operations at the expense of a possibly very large number of registers. We describe a register allocation algorithm that assigns registers to scalar replaced array references along the critical paths of a computation, in many cases exploiting the opportunity for concurrent memory accesses. Experimental results, for a set of image/signal processing code kernels, reveal that the proposed algorithm leads to a substantial reduction in the number of execution cycles for the corresponding hardware implementation on a contemporary field-programmable-gate-array (FPGA) when compared to other greedy allocation algorithms, in some cases, using even fewer registers.