FPGA architecture for multi-style asynchronous logic [full-adder example]

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture, dedicated to asynchronous logic, and the logic style. The innovative aspects of the architecture are described. Moreover, the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions, thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.