DocumentCode
2586357
Title
Logic design for on-chip test clock generation - implementation details and impact on delay test quality
Author
Beck, Matthias ; Barondeau, Olivier ; Kaibel, Martin ; Poehl, Frank ; Lin, Xijiang ; Press, Ron
Author_Institution
Infineon Technol. AG, Munich, Germany
fYear
2005
fDate
7-11 March 2005
Firstpage
56
Abstract
This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.
Keywords
automatic test pattern generation; design for testability; integrated circuit testing; logic design; logic testing; system-on-chip; ATE; ATPG; SOC; delay test quality; fault coverage; fault pattern count; high frequency clock domains; on-chip high-speed clock generation; on-chip test clock logic design; scan architecture; test vector count reduction; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Clocks; Delay; Logic design; Logic testing; Production; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2005. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2288-2
Type
conf
DOI
10.1109/DATE.2005.199
Filename
1395529
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