Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations

Author

Petrovsky, Alexander A. ; Shkredov, Sergei L.

Author_Institution

Real-Time Syst. Dept., Bialystok Tech. Univ.

fYear

2006

fDate

13-17 Sept. 2006

Firstpage

181

Lastpage

186

Abstract

The results presented in the article are based on a methodology for automatic synthesis of real-time split radix 2-4 parallel-pipeline FFT-processors at structural level. The approach is oriented at reconfigurable FPGA-aware design and allows taking into account real-time application restrictions (input data structure and format, operating frequency, transform size, overall throughput) as well as other design restrictions (CLB-count, area, power dissipation). The considered design examples prove method´s good abilities for hardware optimization. Variants of split radix 2-4 computing element implementation are compared. Switching over from floating point arithmetics to fixed point data and the corresponding accuracy issues are considered

Keywords

digital signal processing chips; fast Fourier transforms; field programmable gate arrays; fixed point arithmetic; floating point arithmetic; logic design; parallel architectures; pipeline processing; real-time systems; reconfigurable architectures; automatic generation; data structure; fixed point arithmetic; floating point arithmetic; hardware core optimization; hardware reconfiguration; real-time split-radix 2-4 parallel-pipeline FFT processor; reconfigurable FPGA-aware design; Concurrent computing; Coprocessors; Field programmable gate arrays; Hardware; Informatics; Parallel processing; Pipelines; Power dissipation; Real time systems; Upper bound;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on

Conference_Location

Bialystok

Print_ISBN

0-7695-2554-7

Type

conf

DOI

10.1109/PARELEC.2006.18

Filename

1698657