DocumentCode
2586419
Title
Statistically aware buffer planning
Author
Garcea, Giuseppe S. ; Van Der Meijs, Nick P. ; van der Kolk, Kees-Jan ; Otten, Ralph H J M
Author_Institution
Fac. of Electr. Eng. & Mech. Comput. Sci., Delft Univ. of Technol., Netherlands
Volume
2
fYear
2004
fDate
16-20 Feb. 2004
Firstpage
1402
Abstract
In this paper, we will develop an analytic approach to estimate the statistical properties (mean and variance) of the performance of a uniformly buffered global IC interconnect, based on the mean and (co)variance of the appropriate design and technology parameters. Compared to other approaches, such as Monte Carlo based approaches, our analytic approach would allow a much tighter design optimization loop and provide a better insight in the factors involved. The model that we use is generic, but in this paper we assume a set of synthetic (not based on actual process data) but realistically large values for the variability of the input parameters. Under these assumptions, it follows that solutions for the area/power/performance tradeoff that are optimal in a deterministic setting, might suffer from excessive variability, potentially leading to a yield problem.
Keywords
circuit optimisation; integrated circuit interconnections; statistics; Monte Carlo methods; buffer planning; buffered global IC interconnect; design optimization loop; integrated circuit; performance variability; statistical properties; Analysis of variance; Appropriate technology; Design optimization; Measurement standards; Monte Carlo methods; Performance analysis; Random variables; Stress; Taylor series; Velocity measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2085-5
Type
conf
DOI
10.1109/DATE.2004.1269107
Filename
1269107
Link To Document