Title :
A Novel nm-grain Poly-si Gate Structure For Reduction Of Cell To Cell Write/erase Tunnel Current Deviation In High Speed Quarter Micron FLASH Memories
Author :
Yugami, J. ; Mine, T.
Author_Institution :
Central Research Laboratory, Hitachi., Ltd. Kokubunji, Tokyo 185, JAPAN
Conference_Titel :
VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on
Print_ISBN :
4-930813-75-1
DOI :
10.1109/VLSIT.1997.623725
