Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors

Author

Griese, B. ; Kettelhoit, B. ; Porrmann, M.

Author_Institution

Dept. of Electr. Eng., Paderborn Univ.

fYear

2006

fDate

13-17 Sept. 2006

Firstpage

214

Lastpage

219

Abstract

Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still flexible coprocessors in embedded processor systems. In this paper we analyze different variants for interfacing reconfigurable hardware from an embedded processor. We describe three different on-chip buses and evaluate their usability for dynamically reconfigurable systems. In addition, we analyze the communication latencies and the speed-up factor of a hardware accelerator for floating point operations for a total of eight different coupling variants

Keywords

coprocessors; embedded systems; field programmable gate arrays; floating point arithmetic; reconfigurable architectures; system buses; system-on-chip; FPGA; dynamically reconfigurable coprocessor; embedded processor system; field programmable gate array; floating point operation; on-chip bus; on-chip interface; Application software; Communication system control; Coprocessors; Delay; Field programmable gate arrays; Hardware; Routing; Software performance; System-on-a-chip; Usability;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on

Conference_Location

Bialystok

Print_ISBN

0-7695-2554-7

Type

conf

DOI

10.1109/PARELEC.2006.36

Filename

1698663