FPGA Chip as a System Master for Hardware Aided Parallel Computing

Author

Pierzchlewski, Jacek ; Sniatala, Pawel ; Nowakowski, Blazej ; Rybarczyk, Andrzej ; Wencel, Wojciech

Author_Institution

Poznan Univ. of Technol.

fYear

2006

fDate

13-17 Sept. 2006

Firstpage

220

Lastpage

226

Abstract

This paper presents prototype board and its operating system dedicated for application specific parallel processing. The proposed architecture consists of two AVR microprocessors, FPGA Spartan3, SRAM and flash EEPROM memories, DA converters, and several serial communication ports. To make the system "designer friendly" a supervising algorithm, which can be called as a kind of "operating system" was elaborated. The algorithms were described in VHDL. The Spartan3 FPGA was chosen as a target platform to implement the master controller for the system. Necessary IO devices\´ controllers were implemented in AVRmicro. The designed board with elaborated libraries provides convenient solution to develop dedicated parallel processing systems

Keywords

field programmable gate arrays; hardware description languages; microprocessor chips; parallel processing; AVR microprocessors; DA converter; FPGA Spartan3; FPGA chip; IO device controller; SRAM; VHDL; application specific parallel processing; flash EEPROM memory; hardware aided parallel computing; operating system; prototype board; serial communication port; system master; Communication system control; Computer architecture; EPROM; Field programmable gate arrays; Hardware; Microprocessors; Operating systems; Parallel processing; Prototypes; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on

Conference_Location

Bialystok

Print_ISBN

0-7695-2554-7

Type

conf

DOI

10.1109/PARELEC.2006.39

Filename

1698664