On statistical timing analysis with inter- and intra-die variations

We highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a number of random variables while accounting for spatial correlations. Our methodology sorts the probability density functions (PDFs) of the critical paths of a circuit based on a confidence-point. We show the mathematical accuracy of our method and also implement a typical program to test it on various benchmarks. We find that the worst-case analysis overestimates path delays by more than 50% and that a path´s probabilistic rank with respect to delay is very different from its deterministic rank.