• DocumentCode
    2586683
  • Title

    On-chip multi-channel waveform monitoring for diagnostics of mixed-signal VLSI circuits

  • Author

    Noguchi, Koichiro ; Nagata, Makoto

  • Author_Institution
    Dept. of Comput. & Syst. Eng., Kobe Univ., Japan
  • fYear
    2005
  • fDate
    7-11 March 2005
  • Firstpage
    146
  • Abstract
    The multi-channel waveform monitoring technique enhances the built-in test and diagnostic capability of mixed-signal VLSI circuits. An 8-channel prototype system incorporates adaptive sample time generation with a 10-bit variable step delay generator and algorithmic digitization with a 10-bit incremental reference voltage generator. The prototype, in a 0.18-μm CMOS technology, demonstrated on-chip waveform acquisition at 40-ps and 200-μV resolutions. The waveforms were as accurate as those by an off-chip measurement technique, while more than 95% reduction of the waste time in waveform monitoring was achieved. The area of 700 μm × 600 μm was occupied by a single waveform acquisition kernel that was shared with eight front-end modules of 60 μm × 200 μm each. The developed on-chip multi-channel waveform monitoring technique is waveform accurate, area efficient, and low cost, which are all requisite factors for a diagnosing methodology toward mixed analog and digital signal integrity in the system-on-chip era.
  • Keywords
    CMOS integrated circuits; VLSI; built-in self test; integrated circuit testing; mixed analogue-digital integrated circuits; system-on-chip; 0.18 micron; 200 micron; 200 muV; 40 ps; 60 micron; 600 micron; 700 micron; CMOS technology; SoC; adaptive sample time generation; algorithmic digitization; built-in test; diagnostics; incremental reference voltage generator; mixed-signal VLSI circuits; on-chip multi-channel waveform monitoring; on-chip waveform acquisition; system-on-chip; variable step delay generator; waveform acquisition kernel; Adaptive systems; Built-in self-test; CMOS technology; Circuits; Delay effects; Monitoring; Prototypes; System-on-a-chip; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2005. Proceedings
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-2288-2
  • Type

    conf

  • DOI
    10.1109/DATE.2005.230
  • Filename
    1395545